DS3065WP datasheet(11/15 Pages) MAXIM

Part #	DS3065WP

Description	3.3V, 8Mb, Nonvolatile SRAM with Clock

Download	15 Pages

Scroll/Zoom	100%

Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

Logo

11 / 15 page

3.3V, 8Mb, Nonvolatile SRAM with Clock

11

Clock Operations

RTC Read Mode

The device executes an RTC read cycle whenever CE

(SRAM chip enable) and WE (write enable) are inactive

(high) and CS (RTC chip select) is active (low). The least

significant four address inputs (A0–A3) define which of

the 16 RTC registers is to be accessed (see Table 3).

Valid data is available to the eight data-output drivers

within tACC (access time) after the last address input

signal is stable, provided that CS and OE (output enable)

access times are also satisfied. If CS and OE access

times are not satisfied, data access must be measured

from the later-occurring signal (CS or OE) and the limit-

ing parameter is either tCO for CS or tOEC for OE rather

than address access.

RTC Write Mode

The device executes an RTC write cycle whenever CE

is inactive (high) and the CS and WE signals are active

(low) after address inputs are stable. The later-occurring

falling edge of CS or WE determines the start of the write

cycle. The write cycle is terminated by the earlier rising

edge of CS or WE. All address inputs must be kept valid

throughout the write cycle. WE must return to the high

state for a minimum recovery time (tWR) before another

cycle can be initiated. The CE and OE control signals

should be kept inactive (high) during RTC write cycles

to avoid bus contention. However, if the output drivers

have been enabled (CS and OE active), WE disables the

outputs in tODW from its falling edge.

Clock Oscillator Mode

The oscillator can be turned off to minimize current

drain from the battery. The OSC bit is the MSB of the

SECONDS register (B7 of F9h). Setting OSC to 1 stops

the oscillator; setting OSC to 0 starts the oscillator. The

initial state of OSC is not guaranteed. When power is

applied for the first time, the OSC bit should be enabled.

Reading the Clock

When reading the RTC data, it is recommended to halt

updates to the external set of double-buffered RTC reg-

isters. This puts the external registers into a static state,

allowing the data to be read without register values

changing during the read process. Normal updates to

the internal registers continue while in this state.

External updates are halted by writing a 1 to the read

bit (R). As long as a 1 remains in the R bit, updating is

inhibited. After a halt is issued, the registers reflect the

RTC count (day, date, and time) that was current at the

moment the halt command was issued. Normal updates

to the external set of registers resume within one second

after the R bit is set to 0 for a minimum of 500Fs. The R bit

must be 0 for a minimum of 500Fs to ensure the external

registers have fully updated.

Setting the Clock

As with a clock read, it is also recommended to halt

updates prior to setting new time values. Setting the write

bit (W) to 1 halts updates of the external RTC registers

8h–Fh. After setting the W bit to 1, the RTC registers can

be loaded with the desired count (day, date, and time)

in BCD format. Setting the W bit to 0 then transfers the

values written to the internal registers and allows normal

clock operation to resume.

Using the Clock Alarm

The alarm settings and control for the device reside

within RTC registers 2h–5h. The INTERRUPTS register

(6h) contains two alarm-enable bits: alarm flag enable

(AE) and alarm in backup-mode enable (ABE).

The alarm can be programmed to activate on a specific

day of the month or repeat every day, hour, minute, or

second. Alarm mask bits AM[4:1] control the alarm mode

(Table 2). Configurations not listed in the table default to

the once-per-second mode to notify the user of an incor-

rect alarm setting.

Table 2. Alarm Mask Bits

AM4

AM3

AM2

AM1

ALARM RATE

1

Once per second

1

0

When seconds match

1

0

When minutes and seconds match

1

0

When hours, minutes, and seconds match

0

When date, hours, minutes, and seconds match

Similar Part No. - DS3065WP

Manufacturer	Part #	Datasheet	Description
Maxim Integrated Produc...	DS3065W	321Kb / 18P	3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock Rev 0; 4/05
Maxim Integrated Produc...	DS3065W-100	321Kb / 18P	3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock Rev 0; 4/05

More results

Similar Description - DS3065WP

Manufacturer	Part #	Datasheet	Description
Maxim Integrated Produc...	DS3065W	321Kb / 18P	3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock Rev 0; 4/05
Dallas Semiconductor	DS1265W	192Kb / 8P	3.3V 8Mb Nonvolatile SRAM
Maxim Integrated Produc...	DS1265W	192Kb / 8P	3.3V 8Mb Nonvolatile SRAM 19-5617; Rev 11/10
Dallas Semiconductor	DS1265W	155Kb / 8P	3.3V 8Mb Nonvolatile SRAM
Maxim Integrated Produc...	DS2065W	180Kb / 12P	3.3V Single-Piece 8Mb Nonvolatile SRAM Rev 0; 1/05
	DS3045W	551Kb / 18P	3.3V Single-Piece 1Mb Nonvolatile SRAM with Clock Rev 0; 6/05
	DS3070W	275Kb / 18P	3.3V Single-Piece 16Mb Nonvolatile SRAM with Clock Rev 1; 10/06
	DS3030W	282Kb / 18P	3.3V Single-Piece 256kb Nonvolatile SRAM with Clock Rev 2; 10/06
Dallas Semiconductor	DS3030W	549Kb / 18P	3.3V Single-Piece 256kb Nonvolatile SRAM with Clock
Maxim Integrated Produc...	DS3050W	555Kb / 18P	3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock Rev 0; 4/05

More results

DS3065WP Datasheet(PDF) 11 Page - Maxim Integrated Products

DS3065WP Datasheet(HTML) 11 Page - Maxim Integrated Products

Similar Part No. - DS3065WP

Similar Description - DS3065WP

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Datasheet Download

Link URL