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S1D2502B01 Datasheet(PDF) 48 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 48 Page - Samsung semiconductor |
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48 / 61 page  VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS S1D2502B01 47 Preliminary • PLL of the S1D2502B01 PLL is composed of the phase detector, charge pump, VCO, and N-divider as 4 sub-blocks. The following is the description of the input/output signals. - HFLB (Input) Horizontal flyback signal is refrence signal of the PLL built in S1D2502B01. The HFLB signal's frequency range is 15 ~ 90kHz, so the PLL block must be a wide range PLL that can cover HFLB's entire frequency range. - VCO (Input) Error signal that passes through an external loop filter is input into VCO. Operation voltage range is 1-4V. You can raise immunity towards external noise by lowering VCO sensitivity. You can do this by making it have the maximum operation voltage range possible in the 5V power voltage. Figure 23. Block Diagram of the PLL Built in S1D2502B01 Phase Detector Charge Pump VCO N-Divider Loop Filter VCO_in (Pin3) Div_out HFLB (Pin32) CP_out (Pin4) VCO_out CP0 CP1 DOT0 DOT1 HF0 HF1 HF2 # Composed of External Components fHFLB < 0.4V > 4.2V ~2us |
Similar Part No. - S1D2502B01 |
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Similar Description - S1D2502B01 |
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