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S1D2502B01 Datasheet(PDF) 32 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 32 Page - Samsung semiconductor |
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32 / 61 page  VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS S1D2502B01 31 Preliminary V-AMP Control Registers - 11 (Row 15, Column 14) CS2 — CS1 (bit1 — bit0) Cut-off offset current control BPW2 — BPW1 (bit4 — bit3) Generated clamp pulse width control To carry out this function, set the CLPS bit to " 0 " BLKP (bit 5) Polarity of horizontral fly back signal If this bit is ’0’, HFLB’s polarity is negative, and if ’1’, it is positive. CLPP (bit 6) Polarity of clamp pulse signal If this bit is ’0’, CLP’s polarity is positive, and if ’1’, it is negative. This bit has meaning only if the CLPS bit is set to ’1’. CLPS (bit 7) Clamp pulse generation enable If this bit is ’0’, clamp signal is made using the HFLB signal, so there is no need to supply the clamp signal. and if ’1’you must supply external clamp signal. V-AMP Control Registers - 12 (Row 15, Column 15) HS9 — HS7 (bit2 — bit 0) HS9 — HS7 bits select OSD raster color 3 to be half tone. To carry out half tone function, set the HT bit to " 1 ". Tabel 4. Register Description (Continued) Registers Bits Description CS2 CS1 Cut-off Offset Current POR 0 0 0 O 0 1 50 µA 1 0 100 µA 1 1 150 µA BPW2 BPW1 Width POR 0 0 0.33 µs 0 1 0.66 µs 1 0 1.00 µs O 1 1 1.33 µs HS9 HS8 HS7 OSD Raster Color 3 POR G R B 0 0 0 0 0 0 Black O 0 0 1 0 0 1 Blue 0 1 0 0 1 0 Red 0 1 1 0 1 1 Magenta 1 0 0 1 0 0 Green 1 0 1 1 0 1 Cyan 1 1 0 1 1 0 Yellow 1 1 1 1 1 1 White |
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