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S1D2502B01 Datasheet(PDF) 29 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 29 Page - Samsung semiconductor |
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29 / 61 page  S1D2502B01 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS 28 Preliminary FBLK bit setting is explained at the figure below. Frame Control Registers — 1 (Row 15, Column 01) CP1, CP0 Charge pump output current control This is the PLL block's internal phase detector output status, converted into current. Refer to PLL control. The output is decided by the combination of these two bits. Figure 11. Character/Raster Signal Part Tabel 4. Register Description (Continued) Registers Bits Description CP1 CP0 Charge Pump Current 0 0 0.50 mA 0 1 0.75 mA 1 0 1.00 mA 1 1 1.25 mA Raster Blue Red Bordering Character Raster Blue Red Green |
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