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S1D2502B01 Datasheet(PDF) 15 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 15 Page - Samsung semiconductor |
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15 / 61 page  S1D2502B01 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS 14 Preliminary NOTES: 1. Absolute maximum rating indicates the limit beyond which damage to the device may occur. 2. Operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the electrical characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. 3. V CC supply pins 11, 13, and 22 must be externally wired together to prevent internal damage during VCC power on/off cycles. 4. The supply current specified is the quiescent current for VCC 1/VCC2 and VCC3 with RL = ∞, The supply current for VCC2 (pin 22) also depends on the output load. 5. Output voltage is dependent on load resistor. Test circuit uses RL = 470 Ω 6. Measure gain difference between any two amplifiers Vin = 700mVpp. 7. When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board without socket is recommended. Video amplifier 50MHz cross talk test also requires this printed circuit board. The reason for a double sided full ground plane PCB is that large measurement variations occur in single sided PCBs. 8. Adjust input frequency from 10MHz (AV max reference level) to the -3dB frequency (f -3dB). 9. Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fin = 50MHz for cross talk 50MHz. 10. A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15kHz. This limit is guaranteed by design. if a lower line rate is used a longer clamp pulse may be required. 11. During the AC test the 4V DC level is the center voltage of the AC output signal. For example. If the output is 4Vpp the signal will swing between 2V DC and 6V DC. 12. These parameters are not tested on each product which is controlled by an internal qualification procedure. 13. The conditions block’s 03, 04, 05... etc. signify sub address’0F03, 0F04, 0F05... etc. 14. Sub address 0F03, 0F05 ~ 0F07: FFH 0F04, 0F08 ~ 0F0C: 80H RGB input = S1, When the ABL input voltage is 0V, the R/G/B’s output voltage is VR/VG/VB and uses the formula ABLR = 20log (VR/V cffR) 15. OSD TST mode = High, CLP operation off, RGB input = S5 (frequency sweep), RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), S5’s frequency 1MHz → 130MHz sweep, -3dB point = 20log (V130MHz/V1MHz) 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H 16. OSD TST mode = High, CLP operation off, RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H R input = S5 (50MHz) CT_50M = 20log (VoutG/VoutR) or 20log (VoutB/VoutR) 17. OSD TST mode = High, CLP operation off, RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H R input = S5 (130MHz) CT_150M = 20log (VoutG/VoutR) or 20log (VoutB/VoutR) |
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