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S1D2502B01 Datasheet(PDF) 13 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 13 Page - Samsung semiconductor |
13 / 61 page ![]() S1D2502B01 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS 12 Preliminary OPERATION TIMINGS Table 8. Operation Timings Parameter Symbol Min Typ Max Unit Input Signal HFLB, VFLB Horizontal flyback signal frequency fHFLB - - 120 kHz Vertical flyback signal frequency fVFLB - - 200 Hz I2C Interface SDA, SCL (Refer to Figure 3) SCL clock frequency fSCL - - 300 kHz Hold time for start condition ths 500 - - ns Set up time for stop condition tsus 500 - - ns Low duration of clock tlow 400 - - ns High duration of clock thigh 400 - - ns Hold time for data thd 0 - - ns Set up time for data tsud 500 - - ns Time between 2 access tss 500 - - ns Fall time of SDA tfSDA - - 20 ns Rise time of both SCL and SDA trSDA - - - ns Figure 3. I2C Bus Timing Diagram SDA SCL ths tsud tss thd thigh tlow tsus |
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