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S1D2502B01 Datasheet(PDF) 51 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 51 Page - Samsung semiconductor |
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51 / 61 page  S1D2502B01 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS 50 Preliminary • PLL Control Bit After configuring an external circuit using the recommended values, carry out programming using the recommended values for frequency range and control bits given in the Table below. (Ref: 800 × 600, C1: 562, R1: 5.6K, R2: 27K, R3: 30M) • Locking Range As you can see the figure below, it is 2.35V that measured voltage at pin-3 to optimize OSD quality. The proper voltage range is 1.5 ~ 3.25V. Table 15. Recommend Values of PLL Control Bit Register Set PLL Control Bit Freq. Range CP1 CP0 FPLL HF2 HF1 HF0 DOT1 DOT0 Hex Below 40kHz 0 0 0 0 1 0 1 1 0B 40 - 50kHz 1 0 0 1 0 0 1 1 93 50 - 70kHz 1 0 0 1 0 1 1 1 97 Above 70kHz 1 0 0 1 1 1 1 1 9F Figure 25. Locking Range 1.625V fmax f0 -2¥ð 1.625V 2¥ð fL fC Locking Range Ve (min) Ve (max) 0.75V 1.5V 2.37V 3.25V 4V |
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