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S1D2502B01 Datasheet(PDF) 49 Page - Samsung semiconductor |
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S1D2502B01 Datasheet(HTML) 49 Page - Samsung semiconductor |
49 / 61 page ![]() S1D2502B01 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS 48 Preliminary - DOT0, 1 (Input) Mode control signal that controls the number of dots per line in the frame control register. There are 4 modes: 320, 480, 640, and 800 dots/line. According to your choice of mode, the OSD_PLL block's N-Divider is controlled by one of ÷320, ÷480, ÷640, or ÷800 Divider. - HF0, 1, 2 (Input) The horizontal Sync frequency information is received from the micro controller through the frame control registers-1's bit C-A. - CP0, 1 (Input) Charge Pump's output sourcing (or sinking) current control pin. This control data is received through frame control registers-1's bits E-D. - VCO_OUT (Output) VCO output that becomes a system clock. It is the OSD R, G, B output signal's dot frequency, and the standard signal for OSD's various timings. Also, it is input into the N-Divider and makes a PLL loop - CP_OUT (Output) Charge Pump circuit's output. input into external loop filter. It becomes one of 3 states according to the standard signal input into the phase detector (HFLB) and the divider output (Div_Out). - HFLB Div_Out is lead: Current sink - HFLB Lag: Current source - HFLB In-Phase: High impedence fclk < 0.4V > 4.2V Rise Time : < 4nS Fall Time : < 4nS |
Similar Part No. - S1D2502B01 |
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Similar Description - S1D2502B01 |
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