RV5C387A datasheet(20/42 Pages) RICOH

Part #	RV5C387A

Description	I2C-bus Real-Time Clock ICs with Voltage Monitoring Function?

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Manufacturer	RICOH [RICOH electronics devices division]

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RV5C387A

PRELIMINARY

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transmission has completed.

The slave side (transmission side) continues to release the SDA pin so that

the master will be able to generate Stop Condition, after falling edge of the SCL 9bit of clock pulses.

SCL

from the master

SDA from

the transmission side

SDA from

the receiving side

1

2

8

9

Acknowledge

signal

Start

Condition

(3) Data Transmission Format in I

2C-Bus

I

2C-Bus has no chip enable signal line. In place of it, each device has a 7bit Slave Address allocated. The

first 1byte is allocated to this 7bit address and to the command (R/W) for which data transmission direction is

designated by the data transmission thereafter.

7bit address is sequentially transmitted from the MSB and 2

and after bytes are read, when 8bit is “H” and when write “L”.

The Slave Address of the RV5C387A is specified at (0110010).

At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However,

if start condition is generated without generating Stop Condition, Repeated Start Condition is met and

transmission / receiving data may be continue by setting the Slave Address again. Use this procedure when

the transmission direction needs to be change during one transmission.

S

A

Data

/A P

Data is written to the slave

from the master

S

0

A

Slave Address

Data

A

A P

When data is read from the

slave immediately after 7bit

addressing from the master

Master to slave

Slave to master

Sr

Repeated Start Condition

P

Stop Condition

A

/A Acknowledge Signal

R/W=1(Read)

(0110010)

Inform read has been completed by not generate

an acknowledge signal to the slave side.

Data

R/W=0(Write)

(0110010)

When

the

transmission

direction is to be changed

during transmission.

Sr

1

0

A

R/W=0(Write)

A

Data

R/W=1(Read)

(0110010)

S

1

A

/A P

Inform read has been completed by not generate

an acknowledge signal to the slave side.

Data

S

Start Condition

(0110010)

Slave Address

Salve Address

Slave Address

Data

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RV5C387A Datasheet(PDF) 20 Page - RICOH electronics devices division

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