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RV5C387A Datasheet(PDF) 9 Page - RICOH electronics devices division |
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RV5C387A Datasheet(HTML) 9 Page - RICOH electronics devices division |
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9 / 42 page  PRELIMINARY RV5C387A 12345 - 9 - 13. FUNCTION DESCRIPTIONS 13.1. Address Mapping Address Register Name D a t a A3A2A1A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Second Counter - *2) S40 S20 S10 S8 S4 S2 S1 1 0 0 0 1 Minute Counter - M40 M20 M10 M8 M4 M2 M1 2 0 0 1 0 Hour Counter - - H20 P ⋅/A H10 H8 H4 H2 H1 3 0 0 1 1 Day-of-week Counter - - - - - W4 W2 W1 4 0 1 0 0 Day-of-month Counter - - D20 D10 D8 D4 D2 D1 5 0 1 0 1 Month Counter and Century Bit /19 ⋅20 - - MO10 MO8 MO4 MO2 MO1 6 0 1 1 0 Year Counter Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 7 0 1 1 1 Oscillation Adjustment Register *3) - F6 F5 F4 F3 F2 F1 F0 8 1 0 0 0 Alarm_W (Minute Register) - WM40 WM20 WM10 WM8 WM4 WM2 WM1 9 1 0 0 1 Alarm_W (Hour Register) - - WH20 WP ⋅/A WH10 WH8 WH4 WH2 WH1 A 1 0 1 0 Alarm_W (Day-of-week Register) - WW6 WW5 WW4 WW3 WW2 WW1 WW0 B 1 0 1 1 Alarm_D (Minute Register) - DM40 DM20 DM10 DM8 DM4 DM2 DM1 C 1 1 0 0 Alarm_D (Hour Register) - - DH20 DP ⋅/A DH10 DH8 DH4 DH2 DH1 D 1 1 0 1 - - - - - - - - E 1 1 1 0 Control Register 1 *3) WALE DALE /12 ⋅24 /CLEN2 TEST CT2 CT1 CT0 F 1 1 1 1 Control Register 2 *3) VDSL VDET SCRA- TCH XSTP /CLEN1 CTFG WAFG DAFG Notes: * 1) All the data listed above accept both reading and writing. * 2) The data marked with "-" is invalid for writing and reset to 0 for reading. * 3) When the XSTP bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the XSTP bit. |
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Similar Description - RV5C387A |
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