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R5F64166HDFB Datasheet(PDF) 58 Page - Renesas Technology Corp |
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R5F64166HDFB Datasheet(HTML) 58 Page - Renesas Technology Corp |
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58 / 98 page  REJ03B0253-0110 Rev.1.10 Page 58 of 95 Jun 23, 2010 R32C/116 Group 5. Electrical Characteristics Note: 1. The device is operationally guaranteed under these operating conditions. Figure 5.1 Clock Cycle Time Table 5.5 Operating Conditions (4/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) (1) Symbol Characteristic Value Unit Min. Typ. Max. f(XIN) Main clock oscillator frequency 416 MHz f(XRef) Reference clock frequency 24 MHz f(PLL) PLL clock oscillator frequency 96 128 MHz f(Base) Base clock frequency High speed 64 MHz Normal speed 50 MHz tc(Base) Base clock cycle time High speed 15.625 ns Normal speed 20 ns f(CPU) CPU operating frequency High speed 64 MHz Normal speed 50 MHz tc(CPU) CPU clock cycle time High speed 15.625 ns Normal speed 20 ns f(BCLK) Peripheral bus clock operating frequency High speed 32 MHz Normal speed 25 MHz tc(BCLK) Peripheral bus clock cycle time High speed 31.25 ns Normal speed 40 ns f(PER) Peripheral clock source frequency 32 MHz f(XCIN) Sub clock oscillator frequency 32.768 62.5 kHz Base clock (Internal signal) t c(Base) Peripheral bus clock (Internal signal) t c(BCLK) CPU clock (Internal signal) t c(CPU) |
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