SC16IS752 datasheet(9/59 Pages) NXP

Part #	SC16IS752

Description	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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9 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

9 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.1 Auto-RTS

Figure 5 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS

are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in

TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The

sending device (for example, another UART) may send an additional character after the

trigger level is reached (assuming the sending UART has another character to send)

because it may not recognize the deassertion of RTS until it has begun sending the

additional character. RTS is automatically reasserted once the receiver FIFO reaches the

resume trigger level programmed via TCR[7:4]. This reassertion allows the sending

device to resume transmission.

Fig 4.

Auto ﬂow control (Auto-RTS and Auto-CTS) example

RX

FIFO

FLOW

CONTROL

TX

FIFO

PARALLEL

TO SERIAL

TX

FIFO

RX

FIFO

UART 1

UART 2

RX

TX

RTS

CTS

TX

RX

CTS

RTS

002aab656

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1.

Fig 5.

RTS functional timing

start

character

N

start

character

N + 1

start

stop

RX

RTS

receive

FIFO

read

N

N + 1

12

002aab040

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