SC16IS752 datasheet(8/59 Pages) NXP

Part #	SC16IS752

Description	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

8 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.

Functional description

The UART will perform serial-to-I2C-bus conversion on data characters received from

peripheral devices or modems, and I2C-bus-to-serial conversion on data characters

transmitted by the host. The complete status of the SC16IS752/SC16IS762 UART can be

read at any time during functional operation by the host.

The SC16IS752/SC16IS762 can be placed in an alternate mode (FIFO mode) relieving

the host of excessive software overhead by buffering received/transmitted characters.

Both the receiver and transmitter FIFOs can store up to 64 characters (including three

additional bits of error status per character for the receiver FIFO) and have selectable or

programmable trigger levels.

The SC16IS752/SC16IS762 has selectable hardware ﬂow control and software ﬂow

control. Hardware ﬂow control signiﬁcantly reduces software overhead and increases

system efﬁciency by automatically controlling serial data ﬂow using the RTS output and

CTS input signals. Software ﬂow control automatically controls data ﬂow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216

− 1).

7.1 Trigger levels

The SC16IS752/SC16IS762 provides independently selectable and programmable trigger

levels for both receiver and transmitter interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of

one character. The selectable trigger levels are available via the FIFO Control Register

(FCR). The programmable trigger levels are available via the Trigger Level Register (TLR).

If TLR bits are cleared, then selectable trigger level in FCR is used. If TLR bits are not

cleared, then programmable trigger level in TLR is used.

7.2 Hardware ﬂow control

Hardware ﬂow control is comprised of Auto-CTS and Auto-RTS (see Figure 4). Auto-CTS

and Auto-RTS can be enabled/disabled independently by programming EFR[7:6].

With Auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive

data and de-activates the RTS output when the RX FIFO is sufﬁciently full. The halt and

resume trigger levels in the Transmission Control Register (TCR) determine the levels at

which RTS is activated/deactivated. If TCR bits are cleared, then selectable trigger levels

in FCR are used in place of TCR.

If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun

errors are eliminated during hardware ﬂow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

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