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SC16IS752 Datasheet(PDF) 46 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 46 Page - NXP Semiconductors |
46 / 59 page ![]() SC16IS752_SC16IS762_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 19 May 2008 46 of 59 NXP Semiconductors SC16IS752/SC16IS762 Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Fig 21. SCL delay after reset 002aab437 RESET SCL td15 tw(rst) Rise and fall times refer to VIL and VIH. Fig 22. I2C-bus timing diagram SCL SDA tHD;STA tSU;DAT tHD;DAT tf tBUF tSU;STA tLOW tHIGH tVD;ACK 002aab489 tSU;STO protocol START condition (S) bit 7 MSB (A7) bit 6 (A6) bit 0 LSB (R/W) acknowledge (A) STOP condition (P) 1/fSCL tr tVD;DAT tSP Fig 23. Write to output 002aab255 A W SDA A GPIOn DATA A IOSTATE REG. SLAVE ADDRESS A td1 Fig 24. Modem input pin interrupt 002aab256 A W SDA A R IRQ td2 S A DATA A ACK to master SLAVE ADDRESS MSR REGISTER SLAVE ADDRESS A td3 MODEM pin |
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