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SC16IS752 Datasheet(PDF) 41 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 41 Page - NXP Semiconductors |
41 / 59 page ![]() xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x R/W = 0; A[3:0] = register address; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B a. Register write R/W = 1; A[3:0] = register address; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B b. Register read R/W = 0; A[3:0] = 0000; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B c. FIFO write cycle R/W = 1; A[3:0] = 0000; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B d. FIFO read cycle (1) Last bit (D0) of the last byte to be written to the transmit FIFO. (2) Last bit (D0) of the last byte to be read from the receive FIFO. Fig 20. SPI operation SI A1 A2 A3 R/W SCLK CH1 A0 X CH0 D6 D7 D4 D5 D2 D3 D0 D1 002aab433 SI A1 A2 A3 R/W SCLK CH1 A0 X CH0 002aab434 SO D6 D7 D4 D5 D2 D3 D0 D1 SI A1 A2 A3 R/W SCLK CH1 A0 X CH0 D6 D7 D4 D5 D2 D3 D0 D1 002aab435 D6 D7 D4 D5 D2 D3 D0 D1 last bit(1) SI A1 A2 A3 R/W SCLK CH1 A0 X CH0 002aab436 SO D6 D7 D4 D5 D2 D3 D0 D1 D0 D1 last bit(2) D6 D7 D4 D5 D2 D3 |
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