SC16IS752 datasheet(36/59 Pages) NXP

Part #	SC16IS752

Description	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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Manufacturer	NXP [NXP Semiconductors]

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36 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

36 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

A slave receiver must generate an acknowledge after the reception of each byte, and a

master must generate one after the reception of each byte clocked out of the slave

transmitter. When designing a system, it is necessary to take into account cases when

acknowledge is not received. This happens, for example, when the addressed device is

busy in a real-time operation. In such a case the master, after an appropriate ‘time-out’,

should abort the transfer by generating a STOP condition, allowing other transfers to take

place. These ‘other transfers’ could be initiated by other masters in a multimaster system,

or by this same master.

There are two exceptions to the ‘acknowledge after every byte’ rule. The ﬁrst occurs when

a master is a receiver: it must signal an end of data to the transmitter by not signalling an

acknowledge on the last byte that has been clocked out of the slave. The acknowledge

related clock generated by the master should still take place, but the SDA line will not be

pulled down. In order to indicate that this is an active and intentional lack of

acknowledgement, we shall term this special condition as a ‘negative acknowledge’.

The second exception is that a slave will send a negative acknowledge when it can no

longer accept additional data bytes. This occurs after an attempted transfer that cannot be

accepted.

Fig 14. Data transfer on the I2C-bus

S

P

SDA

SCL

MSB

0

1

6

7

8

0

1

2 to 7

8

ACK

002aab012

START

condition

STOP

condition

acknowledgement signal

from receiver

byte complete,

interrupt within receiver

clock line held LOW

while interrupt is serviced

Fig 15. Acknowledge on the I2C-bus

S

01

6

7

8

002aab013

data output

by transmitter

data output

by receiver

SCL from master

START

condition

transmitter stays off of the bus

during the acknowledge clock

acknowledgement signal

from receiver

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