SC16IS752 datasheet(33/59 Pages) NXP

Part #	SC16IS752

Description	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

33 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.21 Enhanced Features Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 31 shows

the Enhanced Features Register bit settings.

9.

RS-485 features

9.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR bit 1, or if hardware ﬂow control is enabled, the

logic state of the RTS pin is controlled by the hardware ﬂow control circuitry. EFCR

register bit 4 will take the precedence over the other two modes; once this bit is set, the

transmitter will control the state of the RTS pin. The transmitter automatically asserts the

RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin

(logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware ﬂow

control function.

9.2 RS-485 RTS output inversion

EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.

When the transmitter has data to be sent it deasserts the RTS pin (logic 1), and when the

last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

Table 31.

Enhanced Features Register bits description

Bit

Symbol

Description

7

EFR[7]

CTS ﬂow control enable.

logic 0 = CTS ﬂow control is disabled (normal default condition)

logic 1 = CTS ﬂow control is enabled. Transmission will stop when a

HIGH signal is detected on the CTS pin.

6

EFR[6]

RTS ﬂow control enable.

logic 0 = RTS ﬂow control is disabled (normal default condition)

logic 1 = RTS ﬂow control is enabled. The RTS pin goes HIGH when

the receiver FIFO halt trigger level TCR[3:0] is reached, and goes

LOW when the receiver FIFO resume transmission trigger level

TCR[7:4] is reached.

5

EFR[5]

Special character detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. Received data is compared

with Xoff2 data. If a match occurs, the received data is transferred to

FIFO and IIR[4] is set to a logical 1 to indicate a special character has

been detected.

4

EFR[4]

Enhanced functions enable bit.

logic 0 = disables enhanced functions and writing to IER[7:4],

FCR[5:4], MCR[7:5].

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and

MCR[7:5] so that they can be modiﬁed.

3:0

EFR[3:0]

Combinations of software ﬂow control can be selected by programming

these bits. See Table 3 “Software ﬂow control options (EFR[3:0])”.

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