SC16IS752 datasheet(28/59 Pages) NXP

Part #	SC16IS752

Description	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

28 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.9 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the

modem, data set, or peripheral device to the host. It also indicates when a control input

from the modem changes state. Table 21 shows Modem Status Register bit settings per

channel.

Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.

8.10 Scratchpad Register (SPR)

The SC16IS752/SC16IS762 provides a temporary data register to store 8 bits of user

information.

Table 21.

Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD (active HIGH, logical 1). If GPIO6 or GPIO2 is selected as CD

modem pin through IOControl register bit 1 or bit 2, the state of CD pin

can be read from this bit. This bit is the complement of the CD input.

Reading IOState bit 6 or bit 2 does not reﬂect the true state of CD pin.

6

MSR[6]

RI (active HIGH, logical 1). If GPIO7 or GPIO3 is selected as RI modem

pin through IOControl register bit 1 or bit 2, the state of RI pin can be

read from this bit. This bit is the complement of the RI input. Reading

IOState bit 7 or bit 3 does not reﬂect the true state of RI pin.

5

MSR[5]

DSR (active HIGH, logical 1). If GPIO4 or GPIO0 is selected as DSR

modem pin through IOControl register bit 1 or bit 2, the state of DSR pin

can be read from this bit. This bit is the complement of the DSR input.

Reading IOState bit 4 or bit 0 does not reﬂect the true state of DSR pin.

4

MSR[4]

CTS (active HIGH, logical 1). This bit is the complement of the CTS

input.

3

MSR[3]

∆CD. Indicates that CD input has changed state. Cleared on a read.

2

MSR[2]

∆RI. Indicates that RI input has changed state from LOW to HIGH.

Cleared on a read.

1

MSR[1]

∆DSR. Indicates that DSR input has changed state. Cleared on a read.

0

MSR[0]

∆CTS. Indicates that CTS input has changed state. Cleared on a read.

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