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SC16IS752 Datasheet(PDF) 26 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 26 Page - NXP Semiconductors |
26 / 59 page ![]() SC16IS752_SC16IS762_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 19 May 2008 26 of 59 NXP Semiconductors SC16IS752/SC16IS762 Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.7 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 19 shows Modem Control Register bit settings. [1] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable. Table 19. Modem Control Register bits description Bit Symbol Description 7 MCR[7][1] Clock divisor. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6][1] IrDA mode enable. logic 0 = normal UART mode logic 1 = IrDA mode 5 MCR[5][1] Xon Any. logic 0 = disable Xon Any function logic 1 = enable Xon Any function 4 MCR[4] Enable loopback. logic 0 = normal operating mode logic 1 = enable local Loopback mode (internal). In this mode the MCR[1:0] signals are looped back into MSR[4:5] and the TX output is looped back to the RX input internally. 3 MCR[3] reserved 2 MCR[2] TCR and TLR enable. logic 0 = disable the TCR and TLR register logic 1 = enable the TCR and TLR register 1 MCR[1] RTS logic 0 = force RTS output to inactive (HIGH) logic 1 = force RTS output to active (LOW). In Loopback mode, controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled by hardware flow control. 0 MCR[0] DTR. If GPIO5 or GPIO1 is selected as DTR modem pin through IOControl register bit 1 or bit 2, the state of DTR pin can be controlled as below. Writing to IOState bit 5 or bit 1 will not have any effect on the DTR pin. logic 0 = force DTR output to inactive (HIGH) logic 1 = force DTR output to active (LOW) |
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