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SC16IS752 Datasheet(PDF) 25 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 25 Page - NXP Semiconductors |
25 / 59 page SC16IS752_SC16IS762_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 19 May 2008 25 of 59 NXP Semiconductors SC16IS752/SC16IS762 Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = logic 1). logic 0 = parity is not forced (normal default condition). LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data. 4 LCR[4] Parity type select. logic 0 = odd parity is generated (if LCR[3] = logic 1) logic 1 = even parity is generated (if LCR[3] = logic 1) 3 LCR[3] Parity enable. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during transmission and the receiver checks for received parity 2 LCR[2] Number of Stop bits. Specifies the number of stop bits. 0 to 1 stop bit (word length = 5, 6, 7, 8) 1 to 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 18). Table 16. LCR[5] parity selection LCR[5] LCR[4] LCR[3] Parity selection X X 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ‘1’ 1 1 1 forced parity ‘0’ Table 17. LCR[2] stop bit length LCR[2] Word length (bits) Stop bit length (bit times) 0 5, 6, 7, 8 1 15 11 ⁄2 1 6, 7, 8 2 Table 18. LCR[1:0] word length LCR[1] LCR[0] Word length (bits) 005 016 107 118 Table 15. Line Control Register bits description …continued Bit Symbol Description |
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