SC16IS752 datasheet(24/59 Pages) NXP

Part #	SC16IS752

Description	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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Manufacturer	NXP [NXP Semiconductors]

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24 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

24 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.5 Interrupt Identiﬁcation Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a

prioritized manner. Table 13 shows Interrupt Identiﬁcation Register bit settings.

[1]

Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState

register.

8.6 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop

bits, and parity type are selected by writing the appropriate bits to the LCR. Table 15

shows the Line Control Register bit settings.

Table 13.

Interrupt Identiﬁcation Register bits description

Bit

Symbol

Description

7:6

IIR[7:6]

Mirror the contents of FCR[0].

5:1

IIR[5:1]

5-bit encoded interrupt. See Table 14.

0

IIR[0]

Interrupt status.

logic 0 = an interrupt is pending

logic 1 = no interrupt is pending

Table 14.

Interrupt source

Priority

level

IIR[5]

IIR[4]

IIR[3]

IIR[2]

IIR[1]

IIR[0]

Source of the interrupt

1

0

1

0

Receive Line Status error

2

0

1

0

Receiver time-out interrupt

2

0

1

0

RHR interrupt

3

0

1

0

THR interrupt

4

0

modem interrupt[1]

5

1

0

input pin change of state[1]

6

0

1

0

received Xoff signal/special

character

7

1

00000

CTS, RTS change of state

from active (LOW) to

inactive (HIGH)

Table 15.

Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Break control bit. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0 state).

This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 to alert the

communication terminal to a line break condition

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