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SC16IS752 Datasheet(PDF) 20 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 59 page  xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 10. SC16IS752/SC16IS762 internal registers Register address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W General register set[1] 0x00 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R 0x00 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W 0x01 IER CTS interrupt enable[2] RTS interrupt enable[2] Xoff[2] Sleep mode[2] modem status interrupt receive line status interrupt THR empty interrupt RX data available interrupt R/W 0x02 FCR RX trigger level (MSB) RX trigger level (LSB) TX trigger level (MSB)[2] TX trigger level (LSB)[2] reserved[3] TX FIFO reset[4] RX FIFO reset[4] FIFO enable W 0x02 IIR[5] FIFO enable FIFO enable interrupt priority bit 4[2] interrupt priority bit 3[2] interrupt priority bit 2 interrupt priority bit 1 interrupt priority bit 0 interrupt status R 0x03 LCR divisor latch enable set break set parity even parity parity enable stop bit word length bit 1 word length bit 0 R/W 0x04 MCR clock divisor[2] IrDA mode enable[2] Xon Any[2] loopback enable reserved[3] TCR and TLR enable[2] RTS DTR (IO5) R/W 0x05 LSR FIFO data error THR and TSR empty THR empty break interrupt framing error parity error overrun error data in receiver R 0x06 MSR CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS R 0x07 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0x06 TCR[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0x07 TLR[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0x08 TXLVL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R 0x09 RXLVL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R 0x0A IODir[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0x0B IOState[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0x0C IOIntEna [7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0x0D reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] 0x0E IOControl[7] reserved[3] reserved[3] reserved[3] reserved[3] UART software reset I/O[3:0] or RIB, CDB, DTRB, DSRB I/O[7:4] or RIA, CDA, DTRA, DSRA latch R/W 0x0F EFCR IrDA mode (slow/ fast)[8] reserved[3] auto RS-485 RTS output inversion auto RS-485 RTS direction control reserved[3] transmitter disable receiver disable 9-bit mode enable R/W |
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