Electronic Components Datasheet Search |
|
CDCE62005 Datasheet(PDF) 71 Page - Texas Instruments |
|
|
CDCE62005 Datasheet(HTML) 71 Page - Texas Instruments |
71 / 80 page DataConverterJitterRequirements 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 1 10 100 1000 10000 0 2 4 6 8 10 12 14 16 18 20 22 24 26 50fs 100fs 350fs 1ps SERDES CleanedClock Data CDCE 62005 RecoveredClock ASICClock ASIC CDCE62005 www.ti.com SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010 Figure 45. Data Converter Jitter Requirements CDCE62005 SERDES Startup Mode A common scenario involves a host communicating to a satellite system via a high-speed wired communications link. Typical communications media might be a cable, backplane, or fiber. The reference clock for the satellite system is embedded in the high speed link. This reference clock must be recovered by the SERDES, however, the recovered clock contains unacceptable levels of jitter due to a degradation of SNR associated with transmission over the media. At system startup, the satellite system must self-configure prior to the recovery and cleanup of the reference clock provided by the host. Furthermore, upon loss of the communication link with the host, the satellite system must continue to operate albeit with limited functionality. Figure 46 shows a block diagram of an optical based system with such a mechanism that takes advantage of the features of the CDCE62005: Figure 46. CDCE62005 SERDES Startup Overview The functionality provided by the Smart Multiplexer provides a straightforward implementation of a SERDES clock link. The Auxiliary Input provides a startup clock because it connects to a crystal. The on-chip EEPROM determines the default configuration at power-up; therefore, the CDCE62005 requires no host communication to begin cleaning the recovered clock once it is available. The CDCE62005 immediately begins clocking the satellite components including the SERDES using the crystal as a clock source and a frequency reference. After the SERDES recovers the clock, the CDCE62005 removes the jitter via the on-chip synthesizer/loop filter. The recovered clock from the communications link becomes the frequency reference for the satellite system after the smart multiplexer automatically switches over to it. The CDCE62005 applies the cleaned clock to the recovered clock input on the SERDES; thereby establishing a reliable communications link between host and satellite systems. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 71 Product Folder Link(s) :CDCE62005 |
Similar Part No. - CDCE62005 |
|
Similar Description - CDCE62005 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |