CDCE62005 datasheet(54/80 Pages) TI

Part #	CDCE62005

Description	Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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Manufacturer	TI [Texas Instruments]

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Prescaler

Divider

Output

Divider

Output

Divider

Q

SET

CLR

D

~ 6usdelay

f(refclk)

/SYNC

MUX

0

1

Reg 4, SPIBit 5

Ya

Yb

Feedback

Divider

PFD

Input

Divider

ReferenceInput

VCO

LoopFilter

VCOClockafterPrescalerDivider

SYNC synchronizedtoreferenceinput

Reg 4 SPIBit 5 = “1”, Reg 6 SPIBit 24 = “0”

WhenReg6, SPIBit24= “0”,Reg4SPIBit5= “1” andthe

pulselow-to-hightransitionissynchronizedtothereferenceinput,thedelayofthe

low-to-highpulsetothetoggling

ofsynchronizedoutputsisequaltothepropagationdelayof

signalinsidedevice+phaseerror(onreferenceinputedgetransitionafter

signal)+dividerdelay(2.5clockcyclesof

VCOclockafterprescaler)+delaybetween

andinputtransition. Totaluncertaintyis1clockcycleofVCOclockafterprescaler(uncertaintyirrespectiveofoutputdividevalue)

SYNC

.

OutputClock (outputdivider= 2)

Propagationdelayof SYNC insidedevice

ReferenceInputClock

Dividerdelay

PhaseError(onedgetransitionofreferenceinput)

0

1

F(refclk)

Reg 6, SPIBit 24

CDCE62005

SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010

www.ti.com

Output Synchronization

Figure 32. CDCE62005 SYNC to Output delay variation

Output Synchronization Timing

Synchronization of the outputs is edecuted in several ways:

•

The SYNC pin is forced low and then released (manual sync).

•

By setting and then resetting Register 8, SPI Bit 12.

•

Whenever the output dividers are changed.

The most common way to execute the output synchronization is to toggle the SYNC pin where the outputs are

aligned on a low-to-high pulse on the SYNC after a delay as explained in Figure 32. For having tight control on

the delay variation of the outputs synchronization after a low-to-high pulse on the SYNC pin, the Register 4, SPI

Bit 5 needs to be set to “1”. When Reg 6, SPI Bit 24 = "0", the outputs are synchronized to each other and to the

reference input. In this case, the total delay from SYNC low-to-high pulse to toggling of synchronized outputs is

given in Figure 32.

When Reg 6, SPI Bit 24 = "1", the outputs are synchronized to each other and to the SYNC low-to-high pulse. In

this case, the total delay from SYNC low-to-high pulse to toggling of synchronized outputs is equal to the

propagation delay of SYNC signal inside device + divider delay. Total uncertainty is 1 cycle of VCO clock after

prescaler (uncertainty irrespective of output divide value).

54

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