CDCE62005 datasheet(47/80 Pages) TI

Part #	CDCE62005

Description	Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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360

(

) =

degrees

Stepsize deg

OutputDivideRatio

1

(

)

f

=

ClockIN

Stepsize sec

OutputDivideRatio

/1 - /80

DigitalPhase Adjust (7-bits)

Clock

IN

(fromSmartMUX )

ToOutputBuffer

ClockIN

OutputDivider (noadjust )

OutputDivider (phaseadjust )

StartDivider

360

(

)

11.25 /

32

=

°

Stepsize deg

Step

CDCE62005

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SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010

Digital Phase Adjust

Figure 31 provides an overview of the Digital Phase Adjust feature. The output divider includes a coarse phase

adjust that shifts the divided clock signal that drives the output buffer. Essentially, the Digital Phase Adjust timer

delays when the output divider starts dividing; thereby shifting the phase of the output clock. The phase adjust

resolution is a function of the divide function. Coarse phase adjust parameters include:

•

Number of Phase Delay Steps – the number of phase delay steps available is equal to the divide ratio

selected. For example, if a Divide by 4 is selected, then the Digital Phase Adjust can be programmed to

select when the output divider changes state based upon selecting one of the four counts on the input.

Figure 31 shows an example of divide by 16 in which there are 16 rising edges of Clock IN at which the

output divider changes state (this particular example shows the fourth edge shifting the output by one fourth

of the period of the output).

•

Phase Delay Step Size – the step size is determined by the number of phase delay steps according to the

following equations:

(4)

(5)

Figure 31. CDCE62005 Phase Adjust

Phase Adjust example

Given:

Output Frequency: 30.72 MHz

VCO Operating Frequency: 1966.08 MHz

Prescaler Divider Setting: 2

Output Divider Setting: 32

(6)

The tables that follow provide a list of valid register settings for the digital phase adjust blocks.

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