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CDCE62005 Datasheet(PDF) 45 Page - Texas Instruments

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Part # CDCE62005
Description  Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCE62005 Datasheet(HTML) 45 Page - Texas Instruments

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OutputDivider (7-bits)
DigitalPhase Adjust (7-bits)
Sync
Pulse
(internallygenerated )
Enable
From
Output
MUX
To
Output
Buffer
20
Registers 0 - 4
6
Registers 0 - 4
7
8
9
10
11
12
13
Registers 0 - 4
14
15
16
17
18
19
/2-/5
/1 - /8
/2
From
Output
MUX
To
Output
Buffer
16
Registers 0 - 4
Registers 0 - 4
18
19
01
10
00
Prescaler
IntegerDivider
15
17
13
Registers 0 - 4
14
CDCE62005
www.ti.com
SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010
Output Dividers
Figure 29 shows that each output channel provides a 7-bit divider and digital phase adjust block. The Output
Divider Settings lists the divide ratios supported by the output divider for each output channel. Figure 30
illustrates the output divider architecture in detail. The Prescaler provides an array of low noise dividers with duty
cycle correction. The Integer Divider includes a final divide by two stage which is used to correct the duty cycle of
the /1–/8 stage. The output divider’s maximum input frequency is limited to 1.175GHz. If the divider is bypassed
(divide ratio = 1) then the maximum frequency of the output channel is 1.5GHz.
Figure 29. CDCE62005 Output Divider and Phase Adjust
Figure 30. CDCE62005 Output Divider Architecture
Copyright © 2008–2010, Texas Instruments Incorporated
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