CDCE62005 datasheet(44/80 Pages) TI

Part #	CDCE62005

Description	Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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CDCE62005

SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010

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Output Multiplexer Control

The Clock Divider Module receives the clock selected by the output multiplexer. The output multiplexer selects

from one of four clock sources available on the Internal Clock Distribution. For a description of PRI_IN, SEC_IN,

and SMART_MUX, see Figure 23. For a description of SYNTH, see Figure 34.

Table 21. CDCE62005 Output Multiplexer Control Settings

OUTPUT MULTIPLEXER CONTROL

Register n (n = 0,1,2,3,4)

OUTMUXnSELX

OUTMUXnSELY

n.4

n.5

CLOCK SOURCE SELECTED

0

PRI_IN

0

1

SEC_IN

1

0

SMART_MUX

1

SYNTH

Output Buffer Control

Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and

LVCMOS modes. Table 22 lists the settings required to configure the CDCE62005 for each output type.

Registers 0 through 4 correspond to Output Channels 0 through 4 respectively.

Table 22. CDCE62005 Output Buffer Control Settings

OUTPUT BUFFER CONTROL

Register n (n = 0,1,2,3,4)

OUTPUT TYPE

CMOSMODEnPX

CMOSMODEnPY

CMOSMODEnNX

CMOSMODEnNY

OUTBUFSELnX

OUTBUFSELnY

n.22

n.23

n.24

n.25

n.26

n.27

0

1

LVPECL

0

1

0

1

LVDS

See LVCMOS Output Buffer Configuration Settings

0

LVCMOS

0

1

0

1

0

OFF

Output Buffer Control – LVCMOS Configurations

A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each

Output Channel provides a pair of outputs. The CDCE62005 supports four modes of operation for single ended

outputs as listed in Table 23.

Table 23. LVCMOS Output Buffer Configuration Settings

OUTPUT BUFFER CONTROL – LVCMOS CONFIGURATION

Register n (n = 0,1,2,3,4)

Output

Output Mode

Type

CMOSMODEnPX

CMOSMODEnPY

CMOSMODEnNX

CMOSMODEnNY

OUTBUFSELnX

OUTBUFSELnY

n.22

n.23

n.24

n.25

n.26

n.27

X

0

LVCMOS

Negative

Active – Non-inverted

X

0

1

0

LVCMOS

Negative

Hi-Z

X

1

0

LVCMOS

Negative

Active – Non-inverted

X

1

0

LVCMOS

Negative

Low

0

X

0

LVCMOS

Positive

Active – Non-inverted

0

1

X

0

LVCMOS

Positive

Hi-Z

1

0

X

0

LVCMOS

Positive

Active – Non-inverted

1

X

0

LVCMOS

Positive

Low

44

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