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CDCE62005 Datasheet(PDF) 41 Page - Texas Instruments

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Part # CDCE62005
Description  Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCE62005 Datasheet(HTML) 41 Page - Texas Instruments

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PRI _ REF
SEC _ REF
Internal
ReferenceClock
PrimaryClock
SecondaryClock
PrimaryClock
/1:/2:HiZ
/1:/2:HiZ
ReferenceDivider
/1 - /8
PRI_IN
SEC _IN
XTAL /
AUX _IN
Smart
MUX1
Smart
MUX2
SmartMUX
Control
REF_SEL
1
0
Register 0
1
0
Register 1
SmartMultiplexer
AuxiliaryInput
0
1
0
Register 2
Register 3
UniversalInputBuffers
5
4
3
2
Register 5
CDCE62005
www.ti.com
SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010
Smart Multiplexer Auto Mode
Smart Multiplexer Auto Mode switches automatically between clock inputs based on a prioritization scheme
shown in Table 18. If using the Smart Multiplexer Auto Mode, the frequencies of the clock inputs may differ by up
to 20%. The phase relationship between clock inputs has no restriction.
Upon the detection of a loss of signal on the highest priority clock, the smart multiplex switches its output to the
next highest priority clock on the first incoming rising edge of the next highest priority clock. During this switching
operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart
multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of
the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart
multiplexer remains high until the next falling edge as shown in Figure 25.
Figure 25. CDCE62005 Smart Multiplexer Timing Diagram
Smart Multiplexer Dividers
Figure 26. CDCE62005 Smart Multiplexer
The CDCE62005 Smart Multiplexer Block provides the ability to divide the primary and secondary UIB or to
disconnect a UIB from the first state of the smart multiplexer altogether.
Table 19. CDCE62005 Pre-Divider Settings
Primary Pre-Divider
Secondary Pre-Divider
Bit Name
DIV2PRIY
DIV2PRIX
Bit Name
DIV2SECY
DIV2SECX
Register.Bit
0.1
0.0
Divide Ratio
Register.Bit
1.1
1.0
Divide Ratio
0
0
Hi-Z
0
0
Hi-Z
0
1
/2
0
1
/2
1
0
/1
1
0
/1
1
1
Reserved
1
1
Reserved
Copyright © 2008–2010, Texas Instruments Incorporated
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