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CDCE62005 Datasheet(PDF) 33 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 80 page  CDCE62005 www.ti.com SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010 Device Registers: Register 6 Table 12. CDCE62005 Register 6 Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK 0 A0 Address 0 0 1 A1 Address 1 1 2 A2 Address 2 1 3 A3 Address 3 0 4 0 SELVCO VCO Core VCO Select, 0:VCO1(low range), 1:VCO2(high range) EEPROM 5 1 SELPRESCA VCO Core EEPROM PRESCALER Setting. 6 2 SELPRESCB VCO Core EEPROM 7 3 SELFBDIV0 VCO Core EEPROM 8 4 SELFBDIV1 VCO Core EEPROM 9 5 SELFBDIV2 VCO Core EEPROM 10 6 SELFBDIV3 VCO Core EEPROM FEEDBACK DIVIDER Setting 11 7 SELFBDIV4 VCO Core EEPROM 12 8 SELFBDIV5 VCO Core EEPROM 13 9 SELFBDIV6 VCO Core EEPROM 14 10 SELFBDIV7 VCO Core EEPROM 15 11 RESERVED — Must be set to “0” EEPROM If Set to “0” Secondary Input Buffer Internal Termination Enabled 16 12 SEC_TERMSEL Input Buffers EEPROM If set to “1” Secondary Internal Termination circuitry Disabled 17 13 SELBPDIV0 VCO Core EEPROM 18 14 SELBPDIV1 VCO Core BYPASS DIVIDER Setting ( 6 settings + Disable + Enable) EEPROM 19 15 SELBPDIV2 VCO Core EEPROM 20 16 ICPSEL0 VCO Core EEPROM 21 17 ICPSEL1 VCO Core EEPROM CHARGE PUMP Current Select 22 18 ICPSEL2 VCO Core EEPROM 23 19 ICPSEL3 VCO Core EEPROM 24 20 RESERVED VCO Core When set to "0", outputs are synchronized to the reference input on the low-to-high EEPROM pulse on SYNC pin or bit. When set to "1", outputs are synchronized to the SYNC low-to-high pulse 25 21 CPPULSEWIDTH VCO Core If set to 1=wide pulse, 0=narrow pulse EEPROM Enable VCO Calibration Command. To execute this command a rising edge must be generated (i.e. Write a LOW followed by a high to this bit location). This will initiate a 26 22 ENCAL VCO Core EEPROM VCO calibration sequence only if Calibration Mode = Manual Mode (i.e. Register 6 bit 27 is HIGH). 27 23 RESERVED — Must be set to “0” EEPROM 28 24 AUXOUTEN Output AUX Enable Auxiliary Output when set to “1”. EEPROM Select the Output that will driving the AUX Output; 29 25 AUXFEEDSEL Output AUX EEPROM Low for Selecting Output Divider “2” and High for Selecting Output Divider “3” When Set to “1” External Loop filter is used. 30 26 EXLFSEL VCO Core EEPROM When Set to “0” Internal Loop Filter is used. 1: Calibration Mode = Manual Mode. In this mode, a calibration will be initiated if a rising PLL edge is asserted on ENCAL (Register 6 Bit 22). 31 27 ENCAL_MODE EEPROM Calibration 0: Calibration Mode = Startup Mode. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Link(s) :CDCE62005 |
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