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CDCE62005 Datasheet(PDF) 32 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 80 page  CDCE62005 SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010 www.ti.com Device Registers: Register 5 Table 11. CDCE62005 Register 5 Bit Definitions SPI RAM BIT NAME RELATED DESCRIPTION/FUNCTION BIT BIT BLOCK 0 A0 Address 0 1 1 A1 Address 1 0 2 A2 Address 2 1 3 A3 Address 3 0 Input Buffer Select (LVPECL,LVDS or LVCMOS) 4 0 INBUFSELX INBUFSELX EEPROM XY(01 ) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin 5 1 INBUFSELY INBUFSELY EEPROM 6 2 PRISEL WHEN EECLKSEL = 1; EEPROM Bit (6,7,8) 100 – PRISEL, 010 – SECSEL , 001 – AUXSEL 7 3 SECSEL EEPROM 110 – Auto Select ( PRI then SEC) Smart MUX 111 – Auto Select ( PRI then SEC and then AUX) 8 4 AUXSEL EEPROM When EECLKSEL = 0, REF_SEL pin determines the Reference Input to the Smart Mux circuitry. If EEPROM Clock Select Input is set to “1” The Clock selections follows internal EEPROM 9 5 EECLKSEL Smart MUX settings and ignores REF_SEL Pin status, when Set to “0” REF_SEL is used to control EEPROM the Mux, Auto Select Function is not available and AUXSEL is not available. 10 6 ACDCSEL Input Buffers If Set to “1” DC Termination, If set to “0” AC Termination EEPROM Input Buffers If Set to “1” Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be 7 HYSTEN EEPROM 11 disabled. If Set to “0” Primary Input Buffer Internal Termination Enabled 12 8 PRI_TERMSEL Input Buffers EEPROM If set to “1” Primary Internal Termination circuitry Disabled 13 9 PRIINVBB Input Buffers If Set to “1” Primary Input Negative Pin Biased with Internal VBB Voltage. EEPROM 14 10 SECINVBB Input Buffers If Set to “1” Secondary Input Negative Pin Biased with Internal VBB Voltage EEPROM If Set to “1” Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling 15 11 FAILSAFE Input Buffers EEPROM only. 16 12 RESERVED Must be set to “0” EEPROM 17 13 RESERVED -------- Must be set to “0” EEPROM 18 14 SELINDIV0 VCO Core EEPROM 19 15 SELINDIV1 VCO Core EEPROM 20 16 SELINDIV2 VCO Core EEPROM 21 17 SELINDIV3 VCO Core EEPROM INPUT DIVIDER Settings 22 18 SELINDIV4 VCO Core EEPROM 23 19 SELINDIV5 VCO Core EEPROM 24 20 SELINDIV6 VCO Core EEPROM 25 21 SELINDIV7 VCO Core EEPROM 26 22 LOCKW(0) PLL Lock LOCKW(3:0): Lock-detect Window Width EEPROM = 0000 (narrow window), 27 23 LOCKW(1) EEPROM = 0001,0010,0100,0101 ….. 28 24 LOCKW(2) EEPROM = 1110 (widest window) 29 25 LOCKW(3) EEPROM = XX11 (RESERVED) Number of coherent lock events. If set to “0” it triggers after the first lock detection if set to 30 26 LOCKDET PLL Lock EEPROM “1” it triggers lock after 64 cycles of lock detections. 31 27 ADLOCK PLL Lock Selects Digital PLL_LOCK “0” ,Selects Analog PLL_LOCK “1” EEPROM 32 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s) :CDCE62005 |
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