CTRL

GND

C3

L1

Rset

Vin

CTRL

SW

FB

COMP

GND

C1

Vin

C2

LEDsIN

LEDsOut

Minimizethe

areaofthis

trace

Placeenough

VIAsaround

thermalpadto

enhancethermal

performance

P

TPS61165

SLVS790A – NOVEMBER 2007 – REVISED MAY 2010

www.ti.com

LAYOUT CONSIDERATIONS

As for all switching power supplies, especially those high frequency and high current ones, layout is an important

design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.

To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of

high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the

length and area of all traces connected to the SW pin and always use a ground plane under the switching

regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output

capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The

input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC

supply ripple. Figure 16 shows a sample layout.

Figure 16. Layout Recommendation

THERMAL CONSIDERATIONS

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This

using Equation 8:

(8)

junction-to-ambient given in Power Dissipation Table.

The TPS61165 comes in a thermally enhanced QFN package. This package includes a thermal pad that

layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using

thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB

Attachment application report (SLUA271).

16

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