DS641F4

21

CS8421

4.3.4

Muting

The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the

output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is

unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes

invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or

SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft mut-

ed). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock.

Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being

set low, or illegal ratios between OLRCK and the XTI master clock. After all invalid states have been

cleared, the SRC will soft unmute SDOUT.

4.3.5

Group Delay and Phase Matching Between Multiple CS8421 Parts

The equation for the group delay through the sample rate converter is shown in “Digital Filter Character-

istics” on page 12. This phase delay is equal across multiple parts. Therefore, when multiple parts operate

at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched.

4.3.6

Master Clock

The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be sup-

plied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the

typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufactur-

er’s specifications for the external capacitor recommendations. If XTO is not used, such as with a digital

clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 kΩ resistor

to GND.

If either serial audio portis set as master, MCLK will be used to supply the sub-clocks to the master SCLK

and LRCK. In this case, MCLK will be synchronous to the master serial audio port. If both serial audio

ports are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the

clock source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the

XTI clock source is present and valid to ensure proper operation.

When bot h serial ports are configured as slave an d operating at sample rate s les s than 96 kHz, the

CS8421 has the ability to operate wi thout a master clock input through XTI. This benefits the design by

not requiring extra external clock components (lowering production cost) and not requiring a master clock

to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal

oscillator provides the clock to run all of the internal logic. To enable the internal oscillator, simply tie XTI

to GND or VL. In this mode, XTO should be left unconnected.

The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used

to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not

needed, the output of the pin can be disabled by pulling the pin high through a 47 kΩ resistor to VL.

MCLK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low

when disabled by using the internal oscillator mode.