20

DS641F4

CS8421

4.3

Sample Rate Converter (SRC)

Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very

high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a lower

bit depth is selected at the output. The filtering is designed so that a full input audio bandwidth of 20 kHz is

preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the out-

put sample rate becomes less than the input sample rate, the input is automatically band-limited to avoid

aliasing products in the output. Careful design ensures minimum ripple and distortion products are added

to the incoming signal. TheSRC also determines the ratio between the incoming and outgoing sample rates

and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the

dynamic performance of the rate converter and has no influence on the output clock.

4.3.1

Data Resolution and Dither

When using the serial audio input port in Left-Justified and I²S Modes, all input data is treated as 32-bits

wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done

using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input

data will be truncated to the bit depth set by SAIF pin setting. If the SAIF bit depth is set to 16-, 20-, or 24-

bits, and the input data is 32-bits wide, truncation distortion will occur. Similarly, in any serial audio input

port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocksinstead of 20 clocks), the input

words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering

mechanism on the input side of the CS8421, and care must be taken to ensure that no truncation occurs.

Dithering is used internally where appropriate inside the SRC block.

The output side of the SRC can be set to 16-, 20-, 24-, or 32-bits. Dithering is applied and is automatically

scaled to the selected output word length. This dither is not correlated between left and right channels.

4.3.2

SRC Locking and Varispeed

The SRC calculates the ratio between the input sample rate and the output sample rate and uses this in-

formation to set up various parameters inside the SRC block. The SRC takes some time to make this cal-

culation, approximately 4200/Fso (87.5 ms at Fso of 48 kHz).

If Fsi is changing, as in a varispeed application, the SRC will track the incoming sample rate. During this

tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the

incoming sample rate is stable, the SRC will return to normal levels of audio quality.The data buffer in the

SRC can overflow if the input sample rate changes at gre ater than 10%/sec. T here is no provision for

varispeed applications where Fso is changing.

The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there

is a change in Fsi or Fso, SRC_UNLOCK will be set high.The SRC_UNLOCK pin will continue to behigh

until the S RC has reacquired

lock and settled,

at wh ich point it will transition low.

When the

SRC_UNLOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to

unmute its output.

4.3.3

Bypass Mode

When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly

to the serial audio output port. No dithering is performed on theoutput data. This mode is ideal for passing

non-audio data through without a sample-rate conversion. ILRCK and OLRCK should be the same sam-

ple rate and synchronous in this mode. The group delay in this mode is greatly reduced from normal SRC

mode as noted in the “Digital Filter Characteristics” on page 12.