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CS8421-CZZ Datasheet(PDF) 1 Page - Cirrus Logic |
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CS8421-CZZ Datasheet(HTML) 1 Page - Cirrus Logic |
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1 / 36 page  Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) http://www.cirrus.com 32-bit, 192-kHz Asynchronous Sample Rate Converter Features 175 dB Dynamic Range –140 dB THD+N No Programming Required No External Master Clock Required Supports Sample Rates up to 211 kHz Input/Output Sample Rate Ratios of 7.5:1 to 1:8 Master Clock Support for 128 x Fs, 256 x Fs, 384 x Fs, and 512 x Fs (Master Mode) 16-, 20-, 24-, or 32-bit Data I/O 32-bit Internal Signal Processing Dither Automatically Applied and Scaled to Output Resolution Flexible 3-wire Serial Digital Audio Input and Output Ports Master and Slave Modes for Both Input and Output Bypass Mode Time Division Multiplexing (TDM) Mode Attenuates Clock Jitter Multiple Device Outputs are Phase Matched Linear Phase FIR Filter Automatic Soft Mute/Unmute +2.5 V Digital Supply (VD) +3.3 V or 5.0 V Digital Interface (VL) Space-saving 20-pin TSSOP and QFN Packages The CS8421 supports sample rates up to 211 kHz and is available in 20-pinTSSOP and QFN packages in both Commercial (-10° to +70° C) a nd Automo tive ( -40° to +85°C) g rades. Th e CDB842 1 Cu stomer Demonstra- tion b oard is a lso availa ble for d evice evalu ation and implementation suggestions. Please see “Ordering In- formation” on page 36 for complete details. Serial Audio Input Time Varying Digital Filters BYPASS Digital PLL Clock Generator ILRCK ISCLK SDIN Sync Info Data Serial Audio Output OLRCK OSCLK SDOUT XTI XTO SRC_UNLOCK 2.5 V (VD) GND RST Sync Info Data Data Level Translators TDM_IN MS_SEL SAIF SAOF Serial Port Mode Decoder MCLK_OUT 3.3 V or 5.0 V (VL) May ‘10 DS641F4 CS8421 |
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