DMOS Microstepping Driver with Translator

and Overcurrent Protection

A4988

19

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

4988-DS

Copyright ©2009-2010, Allegro MicroSystems, Inc.

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-

mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;

nor for any infringement of patents or other rights of third parties which may result from its use.

ET Package, 28-Pin QFN with Exposed Thermal Pad

0.25 +0.05

–0.07

0.50

0.90 ±0.10

C

0.08

29X

SEATING

PLANE

C

A Terminal #1 mark area

B Exposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

For Reference Only; not for tooling use

(reference JEDEC MO-220VHHD-1)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

C Reference land pattern layout (reference IPC7351

QFN50P500X500X100-29V1M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as

necessary to meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal vias at the

exposed thermal pad land can improve thermal dissipation (reference

EIA/JEDEC Standard JESD51-5)

28

2

1

A

28

1

2

PCB Layout Reference View

B

3.15

0.73 MAX

3.15

3.15

3.15

0.30

1

28

0.50

1.15

4.80

4.80

C

5.00 ±0.15

5.00 ±0.15

D

D Coplanarity includes exposed thermal pad and terminals

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www.allegromicro.com