BH1750FVI

Technical Note

6/17

www.rohm.com

2009.04- Rev.B

© 2009 ROHM Co., Ltd. All rights reserved.

●

Timing chart for VCC and DVI power supply sequence

DVI is I

supplied. In DVI 'L' term, internal state is set to Power Down mode.

1) Recommended Timing chart1 for VCC and DVI supply.

2) Timing chart2 for VCC and DVI supply.

( If DVI rises within 1µs after VCC supply )

DVI

Reset Term ( more than 1us )

DVI

Don't care state

ADDR, SDA, SCL is not stable if DVI 'L' term ( 1us ) is not given by systems.

In this case, please connect the resisters ( approximately 100kOhm ) to ADDR without directly

connecting to VCC or GND,

because it is 3 state buffer for Internal testing.

Reset Term ( more than 1us )