BD9853AFV

Technical Note

10/16

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2009.05 - Rev.A

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Selecting the synchronous diode

An extremely low forward voltage Schottky barrier diode should be employed as the synchronous diode.

Selection of the specific diode to be used should be made in conformance with the following relative configurations for

maximum forward current, reverse voltage and diode power dissipation.

・

・

The reverse voltage rating is higher than the VIN value.

・

Power dissipation for the selected diode must be within the rated level.

Synchronous diode power dissipation (Pdi) is expressed in the following formula:

Pdi=Iout(MAX)×tdt×fosc×Vf

Iout(MAX) : maximum load current, tdt： dead time 60ns typ,fosc : oscillation frequency, Vf：forward voltage

Selecting the output/input coil

The output coil and the output capacitor together form a second-order smoothing filter for the switch waveform and provide

the DC output voltage.

If a coil’s inductor value is low, its physical size is minimized, but the penalty is higher ripple current, with lowered efficiency

and an increase in output noise. Conversely, a higher inductor value increases the size of the coil, but lowers the ripple

current and, consequently. the output ripple current.

Generally speaking, ripple current should be between 20% and 50% of output load current. The following equation is used

to calculate the inductor value that corresponds to the ripple current value being employed.

Selecting the input capacitor

The input capacitor is the source of current that flows to the coil via the FET whenever the high side MOSFET is ON. In

selecting an input capacitor, sufficient margin must be provided to accommodate capacitor pressure and the permissible

ripple current.

The expression below defines the effective value of the ripple current to the input capacitor. It should be used in

determining the suitability of the capacitor in providing sufficient margin for the permissible ripple current.

Selecting the output capacitor

The output capacitor should confine ESR and permissible ripple current within a stable region.

Although incorporating a low-ESR capacitor will limit ripple voltage and load fluctuation, it can also hurt the stability of the

feedback network. Therefore, in order to maintain a stable feedback loop when ceramic or other low-ESR capacitors are

employed, special attention must be paid to providing an appropriate phase compensation scheme.

A suitable output capacitor will satisfy the following formula for ESR.

⊿

In addition, use the following formula to determine the effective value of the output capacitance permissible ripple current,

and select a capacitor that allows sufficient margin to accommodate this value.

Setting the soft start time

To prevent output voltage startup overshoot on either channel, the capacitors connected to the SCP/SOFT 1, 2 pins – in a

discharged state at power-on – are gradually charged during a delay interval, thus providing a soft start. The soft start

period is the time from when the standby pins go from LOW to HIGH, starting the charge, to the time that the output

voltage reaches the programmed setting. The soft start time is calculated in the following equation:

tsoft : soft start time, Cscp/soft : SCP/SOFT pin connection capacitance, Isosoft : charge current

L=

⊿

1

××

,

⊿

=

tsoft＝

Isosoft (typ: 2.3μA)[A]

0.8[V] (typ)×Cscp/soft［F］