Technical Note

10/16

BD9018KV

www.rohm.com

2010.02 - Rev.A

○

c

2010 ROHM Co., Ltd. All rights reserved.

FB

R2

A

COMP

Vo

C2

C1

R1

FB

R2

A

COMP

Vo

C2

R1

R3

Fig. 29

1

2π√LC

Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please

choose one of the following methods to add the phase lead.

⑤

Add C to feedback resistor

⑥

Add R3 to aggregator

Fig. 27

Fig. 28

Phase lead fz =

[Hz]

Phase lead fz =

[Hz]

Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.

When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:

Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is

required, but this is different from the approach described in figure ③～⑥, since in this case the LC resonance gives

rise to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can

be implemented.

⑦

Phase compensation provided by secondary (dual) phase lead

Phase lead fz1 =

[Hz]

Phase lead fz2 =

[Hz]

LC resonance frequency fr =

[Hz]

Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.

This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount

of trial-and-error process. There are many factors (The PCB board layout, Output Current, etc.)that can affect

the DCDC characteristics. Please verify and confirm using practical applications.

1

2πC1R1

1

2πC2R3

1

2πR1C1

1

2πR3C2

FB

R2

A

COMP

Vo

C2

R1

R3

C1