ADP1871 datasheet(26/44 Pages) AD

Part #	ADP1871

Description	Synchronous Buck Controller with Constant On-Time and Valley Current Mode

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ADP1870/ADP1871

Rev. 0 | Page 26 of 44

EFFICIENCY CONSIDERATIONS

One of the important criteria to consider in constructing a dc-to-dc

converter is efficiency. By definition, efficiency is the ratio of the

output power to the input power. For high power applications at

load currents up to 20 A, the following are important MOSFET

parameters that aid in the selection process:

•

VGS (TH): the MOSFET support voltage applied between the

gate and the source

•

RDS (ON): the MOSFET on resistance during channel

conduction

•

QG: the total gate charge

•

CN1: the input capacitance of the upper-side switch

•

CN2: the input capacitance of the lower-side switch

The following are the losses experienced through the external

component during normal switching operation:

•

Channel conduction loss (both of the MOSFETs)

•

MOSFET driver loss

•

MOSFET switching loss

•

Body diode conduction loss (lower-side MOSFET)

•

Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due

to the power dissipated through MOSFET channel conduction.

Power loss through the upper-side MOSFET is directly pro-

portional to the duty cycle (D) for each switching period, and

the power loss through the lower-side MOSFET is directly

proportional to 1 − D for each switching period. The selection

of MOSFETs is governed by the amount of maximum dc load

current that the converter is expected to deliver. In particular,

the selection of the lower-side MOSFET is dictated by the

maximum load current because a typical high current application

employs duty cycles of less than 50%. Therefore, the lower-side

MOSFET is in the on state for most of the switching period.

()

[

] 2

1

LOAD

N2(ON)

N1(ON)

N1,N2(CL)

I

R

D

R

D

P

×

−

+

×

=

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The con-

tributing factors are the dc current flowing through the driver

during operation and the QGATE parameter of the external MOSFETs.

(

)

[

]

()

[]

BIAS

REG

lowerFET

SW

REG

BIAS

DR

upperFET

SW

DR

LOSS

DR

I

V

C

f

V

I

V

C

f

V

P

+

×

+

×

=

)

(

where:

CupperFET

is the input gate capacitance of the upper-side MOSFET.

ClowerFET

is the input gate capacitance of the lower-side MOSFET.

IBIAS

is the dc current flowing into the upper- and lower-side drivers.

VDR

is the driver bias voltage (that is, the low input voltage

(VREG) minus the rectifier drop (see Figure 81)).

VREG

is the bias voltage.

fSW

is the controller switching frequency (300 kHz, 600 kHz, and

1.0 MHz)

800

720

640

560

480

400

320

240

160

80

300

1000

900

800

700

600

500

400

SWITCHING FREQUENCY (kHz)

+125°C

+25°C

–40°C

VREG = 2.7V

VREG = 3.6V

VREG = 5.5V

Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency

Switching Loss

The SW node transitions due to the switching activities of the

upper- and lower-side MOSFETs. This causes removal and

replenishing of charge to and from the gate oxide layer of the

MOSFET, as well as to and from the parasitic capacitance

associated with the gate oxide edge overlap and the drain and

source terminals. The current that enters and exits these charge

paths presents additional loss during these transition times. This

loss can be approximately quantified by using the following

equation, which represents the time in which charge enters and

exits these capacitive regions:

tSW-TRANS

= RGATE × CTOTAL

where:

CTOTAL

is the CGD + CGS of the external MOSFET.

RGATE

is the gate input resistance of the external MOSFET.

The ratio of this time constant to the period of one switching cycle

is the multiplying factor to be used in the following expression:

2

-

)

(

×

=

IN

LOAD

SW

TRANS

SW

LOSS

SW

V

I

t

P

or

2

)

(

×

=

IN

LOAD

TOTAL

GATE

SW

LOSS

SW

V

I

C

R

f

P

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