ADP1871 datasheet(20/44 Pages) AD

Part #	ADP1871

Description	Synchronous Buck Controller with Constant On-Time and Valley Current Mode

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ADP1870/ADP1871

Rev. 0 | Page 20 of 44

VIN and VREG be tied together if the VIN pin is subjected to a

2.75 V rail.

Table 5. Power Input and LDO Output Configurations

VIN

VREG

Comments

>5.5 V

Float

Must use the LDO

<5.5 V

Connect to VIN

LDO drop voltage is not

realized (that is, if VIN =

2.75 V, then VREG = 2.75

V)

<5.5 V

Float

LDO drop is realized

Ranges above

and below 5.5

V

Float

LDO drop is realized,

minimum VIN recom-

mendation is 2.95 V

THERMAL SHUTDOWN

The thermal shutdown is a self-protection feature to prevent the

IC from damage due to a very high operating junction temperature.

If the junction temperature of the device exceeds 155°C, the part

enters the thermal shutdown state. In this state, the device shuts off

both the upper- and lower-side MOSFETs and disables the entire

controller immediately, thus reducing the power consumption of

the IC. The part resumes operation after the junction temperature

of the part cools to less than 140°C.

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

Upon startup, one of the first blocks to become active is the RES

detect circuit. This block powers up before soft start begins. It

forces a 0.4 V reference value at the DRVL output (see Figure 68)

and is programmed to identify four possible resistor values: 47 kΩ,

22 kΩ, open, and 100 kΩ.

The RES detect circuit digitizes the value of the resistor at the

DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code

that is used to program four separate gain configurations in the

current-sense amplifier (see Figure 69). Each configuration corre-

sponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V,

24 V/V, respectively (see Table 6 and Table 7). This variable is used

for the valley current-limit setting, which sets up the appropriate

current-sense gain for a given application and sets the compensation

necessary to achieve loop stability (see the Valley Current-Limit

Setting and Compensation Network sections).

DRVH

DRVL

Q1

SW

Q2

RRES

ADP1870/

ADP1871

CS GAIN

PROGRAMMING

Figure 68. Programming Resistor Location

SW

PGND

CS GAIN SET

CS

AMP

ADC

DRVL

RES

0.4V

Figure 69. RES Detect Circuit for Current-Sense Gain Programming

Table 6. Current-Sense Gain Programming

Resistor

ACS

47 kΩ

3 V/V

22 kΩ

6 V/V

Open

12 V/V

100 kΩ

24 V/V

VALLEY CURRENT-LIMIT SETTING

The architecture of the ADP1870/ADP1871 is based on valley

current-mode control. The current limit is determined by three

components: the RON of the lower-side MOSFET, the error ampli-

fier output voltage swing (COMP), and the current-sense gain.

The COMP range is internally fixed at 1.4 V. The current-sense

gain is programmable via an external resistor at the DRVL pin (see

the Programming Resistor (RES) Detect Circuit section). The

RON of the lower-side MOSFET can vary over temperature and

usually has a positive TC (meaning that it increases with tempera-

ture); therefore, it is recommended to program the current-sense

gain resistor based on the rated RON of the MOSFET at 125°C.

Because the ADP1870/ADP1871 are based on valley current

control, the relationship between ICLIM and ILOAD is as follows:

⎟

⎠

⎞

⎜

⎝

⎛ −

×

=

2

1

I

LOAD

CLIM

K

I

where:

KI

is the ratio between the inductor ripple current and the

desired average load current (see Figure 70).

ICLIM

is the desired valley current limit.

ILOAD

is the current load.

Establishing KI helps to determine the inductor value (see the

Inductor Selection section), but in most cases KI = 0.33.

LOAD CURRENT

VALLEY CURRENT LIMIT

RIPPLE CURRENT =

ILOAD

3

Figure 70. Valley Current Limit to Average Current Relation

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