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ADP1871 Datasheet(PDF) 34 Page - Analog Devices |
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ADP1871 Datasheet(HTML) 34 Page - Analog Devices |
34 / 44 page ADP1870/ADP1871 Rev. 0 | Page 34 of 44 OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4. BYPASS POWER CAPACITOR (C1) FOR VREG BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC. SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). Figure 85. Overall Layout of the ADP1870 High Current Evaluation Board |
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