Document:1G5-0147

Rev.1

Page 4

VIS

VG26(V)(S)18165C

1,048,576 x 16 - Bit

CMOS Dynamic RAM

TRUTH TABLE

Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

FUNCTION

RAS

LCAS

UCAS

WE

OE

ADDRESSES

Notes

ROW

COL

STANDBY

H

X

X

X

X

High-Z

READ : WORD

L

L

L

H

L

ROW

COL

Data-Out

READ : LOWER BYTE

L

L

H

H

L

ROW

COL

Lower Byte: Data-Out

Upper Byte: High-Z

READ: UPPER BYTE

L

H

L

H

L

ROW

COL

Lower Byte: High-Z

Upper Byte: Data-Out

WRITE: WORD

(EARLY WRITE)

L

L

L

L

X

ROW

COL

Data-In

WRITE: LOWER

BYTE (EARLY)

L

L

H

L

X

ROW

COL

Lower Byte: Data-In

Upper Byte: High-Z

WRITE : UPPER

BYTE (EARLY)

L

H

L

L

X

ROW

COL

Lower Byte: High-Z

Upper Byte: Data-In

READ WRITE

L

L

L

ROW

COL

Data-Out, Data-In

1,2

PAGE-MODE

READ

1st Cycle

L

H

L

ROW

COL

Data-Out

2

2nd Cycle

L

H

L

n/a

COL

Data-Out

2

PAGE-MODE

WRITE

1st Cycle

L

L

X

ROW

COL

Data-In

1

2nd Cycle

L

L

X

n/a

COL

Data-In

1

PAGE-MODE

READ-

WRITE

1st Cycle

L

ROW

COL

Data-Out, Data-In

1,2

2nd Cycle

L

n/a

COL

Data-Out, Data-In

1,2

HIDDEN

REFRESH

READ

L

L

H

L

ROW

COL

Data-Out

2

WRITE

L

L

L

X

ROW

COL

Data-In

1,3

RAS-ONLY REFRESH

L

H

H

X

X

ROW

n/a

High-Z

CBR REFRESH

L

L

H

X

X

X

High-Z

4

H

X

→

H

X

→

H

L

→

L

H

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

H

L

→

L

H

→

H

L

→

H

L

→

H

L

→

L

H

→

LH

L

→ →

LH

L

→ →

H

L

→