Rev 0.2 / Jan. 2008
47
1
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of
the 1st or 2nd th page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-
nize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flow-
chart shown in Figure 31. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Figure 31: Bad Block Management Flowchart
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