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HY27UF082G2B Datasheet(PDF) 22 Page - Hynix Semiconductor |
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HY27UF082G2B Datasheet(HTML) 22 Page - Hynix Semiconductor |
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22 / 54 page  Rev 0.2 / Jan. 2008 22 1 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash Parameter Symbol 3.3V Unit Min Max CLE Setup time tCLS 12 ns CLE Hold time tCLH 5ns CE setup time tCS 20 ns CE hold time tCH 5ns WE pulse width tWP 12 ns ALE setup time tALS 12 ns ALE hold time tALH 5ns Data setup time tDS 12 ns Data hold time tDH 5ns Write Cycle time tWC 25 ns WE High hold time tWH 10 ns Data Transfer from Cell to register tR 25 us ALE to RE Delay tAR 10 ns CLE to RE Delay tCLR 10 ns Ready to RE Low tRR 20 ns RE Pulse Width tRP 12 ns WE High to Busy tWB 100 ns Read Cycle Time tRC 25 ns RE Access Time tREA 20 ns RE High to Output High Z tRHZ 100 ns CE High to Output High Z tCHZ 50 ns CE High to Output hold tCOH 15 ns RE High to Output Hold tRHOH 15 ns RE Low to Output Hold tRLOH 5ns RE High Hold Time tREH 10 ns Output High Z to RE low tIR 0ns CE Low to RE Low tCR 10 ns Address to data loading time tADL 70 ns WE High to RE low tWHR 60 ns RE High to WE low tRHW 100 ns Device Resetting Time (Read / Program / Erase) tRST 5/10/500(1) us Write Protection time tWW(2) 100 ns Table 13: AC Timing Characteristics NOTE: 1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us 2. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High. |
Similar Part No. - HY27UF082G2B |
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