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HY27UF082G2B Datasheet(PDF) 17 Page - Hynix Semiconductor |
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HY27UF082G2B Datasheet(HTML) 17 Page - Hynix Semiconductor |
17 / 54 page Rev 0.2 / Jan. 2008 17 1 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 4. OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides hardware pro- tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 28. The two-step command sequence for program/erase provides additional software protection. 4.2 Ready/Busy. The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Fig 28). Its value can be determined by the following guidance. |
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