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HY27UF082G2B Datasheet(PDF) 15 Page - Hynix Semiconductor |
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HY27UF082G2B Datasheet(HTML) 15 Page - Hynix Semiconductor |
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15 / 54 page  Rev 0.2 / Jan. 2008 15 1 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 3.8 EDC Operation Error Detection Code check automatically starts immediately after device becomes busy for a copy back program oper- ation (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 bytes, where each 528byte group is composed by 512 bytes of main array and 16 bytes of spare area (see Table 20,21). So described 528byte area is called “EDC unit”. In the x16 version EDC allows detection of 1 single bit error every 264 words, where each 264 word group is composed by 256 words of main array and 8 words of spare area (see Table 20,21). So described 264 word area is called “ EDC unit”. To Properly use EDC, some limitations apply: - Random data input can be used only once in copy back program or page program or multiple page program, unless user inputs data for a whole EDC unit (or more whole EDC units). - Any page program operation must be done on whole page basis, or on whole EDC unit (s). EDC result can be checked only during copy back program through 7Bh (specific Read EDC register command, Table 22) 3.9 Read Status Register The device contains a Status Register which may be read to find out whether, program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, which- ever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connec- tions even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 14 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random data output, the read command (00h) should be given before starting read cycles. 3.10 Read EDC Status Register The operation is available only in copy back program and it allows the detection of errors occurred during read for copy back. In case of multiple plane copy back, it is not possible to know which of the two read operation caused the error. After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. Operation is same read status register command. Refer to below Table 22 for specific EDC Register definitions. 3.11 Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd, 4th, 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 24 shows the operation sequence, while tables 15 explain the byte meaning. 3.12 Reset The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure 27. |
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