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HY27UF082G2B Datasheet(PDF) 11 Page - Hynix Semiconductor |
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HY27UF082G2B Datasheet(HTML) 11 Page - Hynix Semiconductor |
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11 / 54 page  Rev 0.2 / Jan. 2008 11 1 HY27UF(08/16)2G2B Series 2Gbit (256Mx8bit) NAND Flash 2. BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. 2.1 Command Input Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See Figure 6 and Table 13 for details of the timings requirements. Command codes are always applied on IO7:0 regardless of the bus configuration. (x8 or x16) 2.2 Address Input Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses for the 4Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify- ing operation (write/erase) the Write Protect pin must be high. See Figure 7 and Table 13 for details of the timings requirements. Addresses are always applied on IO7:0 regardless of the bus configuration (x8 or x16). 2.3 Data Input Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serial and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 8 and Table 13 for details of the timings requirements. 2.4 Data Output Data Output bus operation allows to read data from the memory array and to check the status register content, the EDC register content and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 9,10,12,13,14 and Table 13 for details of the timings requirements. 2.5 Write Protect Hardware Write Protection is activated when the Write Protect pin is low. In this condition modifying operation does not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protec- tion even during the power up. 2.6 Standby In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. |
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