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HY5PS12421F-E3 Datasheet(PDF) 22 Page - Hynix Semiconductor |
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HY5PS12421F-E3 Datasheet(HTML) 22 Page - Hynix Semiconductor |
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22 / 35 page  Rev. 1.4 / July 2006 22 1HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F * : tRAS(min) , tRC(min) specification for DDR2-400 4-4-4 is 45ns, 60ns respectively. Parameter Symbol DDR2-667 Unit Note min max DQ output access time from CK/CK tAC -450 +450 ps DQS output access time from CK/CK tDQSCK -400 +400 ps CK high-level width tCH 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 tCK CK half period tHP min(tCL, tCH) - ps 11,12 Clock cycle time, CL=x tCK 3000 8000 ps 15 DQ and DM input setup time tDS 50 - ps 6,7,8,20 DQ and DM input hold time tDH 175 - ps 6,7,8,21 Control & Address input pulse width for each input tIPW 0.6 - tCK DQ and DM input pulse width for each input tDIPW 0.35 - tCK Data-out high-impedance time from CK/CK tHZ - tAC max ps 18 DQS low-impedance time from CK/CK tLZ (DQS) tAC min tAC max ps 18 DQ low-impedance time from CK/CK tLZ (DQ) 2*tAC min tAC max ps 18 DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 ps 13 DQ hold skew factor tQHS - 340 ps 12 DQ/DQS output hold time from DQS tQH tHP - tQHS - ps Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 tCK DQS input high pulse width tDQSH 0.35 - tCK DQS input low pulse width tDQSL 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - tCK Mode register set command cycle time tMRD 2 - tCK Write postamble tWPST 0.4 0.6 tCK 10 Write preamble tWPRE 0.35 - tCK Address and control input setup time tIS 150 - ps 5,7,9,22 Address and control input hold time tIH 275 - ps 5,7,9,23 Read preamble tRPRE 0.9 1.1 tCK 19 Read postamble tRPST 0.4 0.6 tCK 19 Activate to precharge command tRAS 45 70000 ns 3 Active to active command period for 1KB page size products tRRD 7.5 - ns 4 Active to active command period for 2KB page size products tRRD 10 - ns 4 Four Active Window for 1KB page size products tFAW 37.5 - ns |
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