Rev. 1.1 / May. 2005

27

Note :

1.

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2.

Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3.

Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).

4.

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

5.

Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

6.

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).

tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and

output pattern effects, and p-channel to n-channel variation of the output drivers.

7.

DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

Signal transitions through the DC region must be monotonic.

Data-In Hold Time to DQS-In (DQ & DM)

0.35

-0.4

-0.4

-0.4

-

ns

3

Read DQS Preamble Time

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

CK

Read DQS Postamble Time

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

CK

Write DQS Preamble Setup Time

0

-

0-0-0-

ns

Write DQS Preamble Hold Time

0.35

-

0.35

-

0.35

-

0.35

-

CK

Write DQS Postamble Time

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

CK

Mode Register Set Delay

2

-

2-2-2-

CK

Exit Self Refresh to Any Execute Command

200

-200

-200

-200

-

CK

4

Power Down Exit Time

2tCK

+ tIS

-

1tCK

+ tIS

-

1tCK

+ tIS

-

1tCK

+ tIS

-

CK

Average Periodic Refresh Interval

-

7.8

-

7.8

-

7.8

-

7.8

us

Parameter

Symbol

33

36

4

5

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max