Rev. 1.1 / May. 2005

7

SIMPLIFIED COMMAND TRUTH TABLE

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

ADDR

A8/

AP

BA

Note

Extended Mode Register Set

H

X

LLLL

OP code

1,2

Mode Register Set

H

X

LLLL

OP code

1,2

Device Deselect

HX

H

XXX

X1

No Operation

L

HHH

Bank Active

H

X

L

L

H

H

RA

V

1

Read

H

X

LHLH

CA

L

V

1

Read with Autoprecharge

H1,3

Write

HX

L

H

L

L

CA

L

V

1

Write with Autoprecharge

H1,4

Precharge All Banks

HX

L

L

H

L

X

HX

1,5

Precharge selected Bank

LV

1

Read Burst Stop

H

X

L

H

H

L

X

1

Auto Refresh

H

H

LLL

H

X

1

Self Refresh

Entry

H

L

LLL

H

X

1

Exit

L

H

H

XXX

1

L

HHH

Precharge Power

Down Mode

Entry

H

L

H

XXX

X

1

L

HHH

1

Exit

L

H

H

XXX

1

L

HHH

1

Active Power

Down Mode

Entry

H

L

H

XXX

X

1

L

VVV

1

Exit

L

H

X

1

Note :

1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )